High-level versus low-level do-loop parallelization: results for one testcase of a multi-block solver on a shared memory parallel vector computer
High-level versus low-level do-loop parallelization: results for one testcase of a multi-block solver on a shared memory parallel vector computer
| dc.contributor.author | Wijnandts, P. | en_US |
| dc.contributor.author | Vogels, M.E.S. | en_US |
| dc.date.accessioned | 2017-02-14T09:46:20Z | |
| dc.date.available | 2017-02-14T09:46:20Z | |
| dc.date.issued | 1997 | en_US |
| dc.identifier.other | NLR-TP-1997-592 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10921/1302 | |
| dc.language.iso | nl | en_US |
| dc.publisher | National Aerospace Laboratory NLR | en_US |
| dc.relation.ispartofseries | NLR Technical Publication;1997-592 | en_US |
| dc.subject.other | Mathematical and computer sciences | en_US |
| dc.subject.other | Numerical analysis | en_US |
| dc.title | High-level versus low-level do-loop parallelization: results for one testcase of a multi-block solver on a shared memory parallel vector computer | en_US |
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